Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure

ABSTRACT

A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to semiconductor circuits and structures.More specifically, this invention relates to a non-aligned MOSFETstructure and process using resistors as the diffusions and capacitorsas the gate for electrostatic discharge (ESD) protection.

[0003] 2. Description of Related Art

[0004] Protection against ESD is a familiar problem in the design ofsemiconductor devices. It is common to use an NMOS FET device in bipolarmode (parasitic npn) with N+ type diffusions for the source and drain,and a channel formed in a P-well in a P-type substrate, as protectionagainst ESD. In an NMOS FET, the source of the FET forms the emitter ofthe bipolar, the FET channel region between drain to source forms thebase, and the drain forms the collector. When electron and holes arecreated by avalanche multiplication at the drain, the holes forward-biasthe base-emitter junction and the parasitic bipolar turns on once thelocal substrate bios meets or exceeds approximately 0.7 volts (vbe).During normal operations, the NPN beneath the FET is turned off. Duringan ESD event, the NPN turns on at a trigger voltage and clamps the ESDvoltage at the protected node (sustaining/holding voltage).

[0005] In today's advanced CMOS technologies, the NFET device used inparasitic bipolar npn mode during an ESD event is of limited use due toits relatively low second trigger current (It2), also known as thermalrunaway current. The parasitic npn emitter consists of only a smallsection of the N-extension/source-drain sidewall due to the highvertical field, thus causing the bipolar action to occur mainly alongthe silicon/SiO2 interface. Since the effective emitter area of thebipolar during avalanche conditions is formed in a shallow region, thecurrent density becomes very large during an avalanche/ESD event andcauses a significant temperature increase in the region.

[0006] The problem with the typical NFET device used for ESD protectionthus becomes twofold. First, the high vertical field causes theemitter/base/collector region of the bipolar to occur at the Si/SiO2surface where the shallow extension region exists. This results in ahigh current density through this region during an ESD event. Second,the lighter doping in the extension region, combined with the highcurrent density during an ESD event, causes a significant increase inthe temperature of the silicon where the bipolar action is occurring,compared to the temperature in that region if the extension is notpresent. The NFET becomes a more efficient ESD device when the dopinglevel and depth of the emitter/collector (extension region) isincreased. This reduces the temperature in the silicon and increases theemitter efficiency in the extension region.

[0007] One way to increase the doping level in the emitter/collector isto eliminate the extension so that the emitter/collector is formed onthe junction side wall instead of the extension side wall. A second wayto reduce the impact of the extension is to form a deeper implant in theextension region.

[0008] Prior publications have disclosed using additional implants thatare implanted at a higher dose/energy than the extension implant. Addingadditional dopant into the extension region at a higher energy than theextension implant, makes the extension deeper and reduces thetemperature in the silicon during an ESD event. The drawback to thisprior art is that the process requires an additional mask.

[0009] The proposed invention increases the doping concentration anddepth of the emitter/collector creating a more efficient bipolar. Thedevice therefore operates at a lower temperature during an ESD event dueto the reduced current density through the higher doped, deeperjunctions which form the emitter/collector regions.

[0010] Bearing in mind the problems and deficiencies of the prior art,it is therefore an object of the present invention to provide a methodand structure to decrease the current density and joule heating in anNFET ESD protection device durng an ESD event.

[0011] It is another object of the present invention to provide a methodand structure of reducing the current density through the shallowemitter area during an ESD event.

[0012] A further object of the invention is to provide a method andstructure to lower the operating temperature of the emitter regionduring an ESD event.

[0013] It is yet another object of the present invention to provide amethod and structure to form the emitter/collector on the junction sidewall instead of the extension side wall.

[0014] It is yet still a further object of the present invention toprovide a method and structure to implant a deeper implant into theextension region.

[0015] Another object of the present invention is to provide a methodand structure to increase the doping level in the emitter/collector andeliminate the extension region.

[0016] Finally, yet another object of the present is to provide a methodand structure to eliminate the need for additional masks in forming anNFET ESD protection device.

[0017] Still other objects and advantages of the invention will in partbe obvious and will in part be apparent from the specification.

SUMMARY OF THE INVENTION

[0018] The above and other objects and advantages, which will beapparent to one of skill in the art, are achieved in the presentinvention which is directed to, in a first aspect, a non-self alignedMOSFET transistor for ESD protection comprising a substrate having asource diffusion region and a drain diffusion region. A first resistorwell is implanted into the source diffusion region on the substrate toform a first resistor well and a second resistor well is implanted intothe drain diffusion region on the substrate to form a second resistorwell. The first and second resistor well have a junction depth extendinginto the substrate which can extend to approximately 0.40 um. In thepreferred embodiment, the depth of each junction is variable. The firstresistor well and second resistor are spaced apart to define a channelregion there between which connects the first and second resistor wells.A gate oxide layer and a gate electrode are deposited on top of thechannel to form a gate. An N-extension mask may be placed over the gateelectrode and implanted into the gate.

[0019] In the preferred embodiment, the gate oxide layer is siliconoxide and the gate electrode is polysilicon. The gate oxide layer andgate electrode extend on top of and overlap the first and secondresistor wells to form first and second overlap regions. It is preferredthat the amount of overlap of the first and second overlap regions isvariable. A variable capacitor may be formed between the gate electrodeand drain diffusion region by the overlap in the second overlap regionand a variable resistor-capacitor controlled network may be formed onthe gate electrode of the MOSFET by the variable capacitor incombination with the first resistor well.

[0020] In another embodiment, a silicide blocking mask can be depositedabove the first and second resistor wells to inhibit the formation ofsilicide and deepen the junction depths of the first and second resistorwells.

[0021] The device may further include a third resistor tub overlying andembedded in the second resistor well to form a resistor ballasted NFET.

[0022] In another aspect, the present invention relates to a method ofmanufacturing a non-self aligned MOSFET transistor for ESD protectioncomprising first providing a substrate having a source diffusion regionand a drain diffusion region. A first resistor tub is implanted into thesource diffusion region forming a first resistor well having a firstjunction depth and a second resistor tub is implanted into the draindiffusion region forming a second resistor well having a second junctiondepth. The depths of the first and second junction depths can extend toapproximately 0.40 um. It is preferred that the junction depths of thefirst and second junctions be variable. The first resistor well isseparated from the second resistor well by a channel region therebetween and a gate oxide layer and gate electrode are deposited over thechannel region to form a gate.

[0023] In the preferred embodiment, the gate oxide layer is siliconoxide and the gate electrode is polysilicon. It is also preferred thatthe gate oxide layer extends onto and overlaps the first and secondresistor wells to define a first and second overlap region.

[0024] In a preferred embodiment, a n-extension mask is formed over thetop of the gate electrode and the mask is implanted into the gate.

[0025] In another aspect, the invention further includes the step, priorto the step of depositing the gate oxide layer and gate electrode, ofdepositing a silicide blocking mask over the first and second resistorwells. The blocking mask inhibits the formation of silicide, therebydeepening the junction depths of the first and second resistor wells.

[0026] The method may further comprise the step of overlying andembedding a third resistor tub in the second resistor well to form aresistor ballasted NFET.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The features of the invention believed to be novel and theelements characteristic of the invention are set forth withparticularity in the appended claims. The figures are for illustrationpurposes only and are not drawn to scale. The invention itself, however,both as to organization and method of operation, may best be understoodby reference to the detailed description which follows taken inconjunction with the accompanying drawings in which:

[0028]FIG. 1 is an elevational view of a semiconductor structure showingthe ESD protection device of this invention.

[0029]FIG. 2 is an elevational view of a semiconductor structure showinga resistor ballasted NFET ESD protection device.

[0030]FIG. 3 is a schematic representation of FIG. 3.

[0031]FIG. 4 is an elevational view of a semiconductor structure showingthe resistor capacitor triggered NFET of this invention.

[0032]FIG. 5 is a schematic representation of FIG. 5.

[0033]FIG. 6 is an elevational view of a semiconductor structure showingthe use of a silicide blocking mask in the formation of the ESDprotection device of this invention.

[0034]FIG. 7 is a schematic representation of FIG. 6.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

[0035] In describing the preferred embodiment of the present invention,reference will be made herein to FIGS. 1-7 of the drawings in which likenumerals refer to like features of the invention. Features of theinvention are not necessarily shown to scale in the drawings.

[0036] The present invention creates a MOSFET like structure for ESDprotection using resistor wells as the diffusions and adjustablecapacitors. The device compensates the shallow extension region withoutthe need for additional masks. The source/drain doping is less than thatof a normal MOSFET but extends deeper into the silicon since the presentinvention uses a resistor well as the source/drain. The deeperemitter/collector increases the second trigger current of the NFET whenused as an ESD protection device.

[0037] As shown in FIG. 1, the present invention provides a MOS deviceusing resistor wells 10, 12 as the MOSFET source 28/drain 30 implants.The device of the present invention may be formed by first implanting afirst resistor well 10 and a second resistor well 12 on a starting wafer24, as shown in FIG. 2, where the starting wafer could be epi, no epi orsilicon on insulator (“SOI”). The first resistor well 10 and secondresistor well 12 are spaced apart to define a channel region 18. Afterimplanting the resistor wells 10, 12, a gate oxide layer 14 and a gateelectrode 16 are deposited on top of the p-type EPI 24 to form gate 32(as shown in FIG. 1). The gate oxide layer may be silicon dioxide andthe gate electrode may be polysilicon. The gate oxide layer 14 and gateelectrode 16 are deposited on top of the channel 18 and extend onto andoverlap the first 10 and second 12 resistor wells. The overlap creates afirst 20 and second 22 overlap region.

[0038] While the embodiment of FIG. 1 illustrates the formation of theresistor wells on a p-type EPI 24 and p+ type bulk substrate 26, orwafer, the resistor wells of the present invention can be formed on anystarting wafer, such as p−, p+, n−, n+ or bulk or SOI CMOS.

[0039] In the conventional process a MOS transistor typically consistsof a gate electrode that has been deposited on a thin dielectric layerover the substrate, with electrically conductive source and drainregions formed in the substrate on opposing sides of the gate electrode.The conductive regions are separated by the channel, a poorly conductiveregion under the gate electrode. Unlike the conventional process offorming a MOSFET, in the present invention the first and second resistorwells are formed first so as to position the resistor wells and createthe overlap. A drawback to the present invention is that it cannot beminimum MOSFET channel length due to the overlay tolerance of theresistor well mask.

[0040] After the gate electrode 32 is formed an N-extension mask 38 canbe placed over the top of the gate electrode 16 and implanted into thegate 32, as shown in FIG. 1. This lightly doped implant 38 into the gateelectrode 32 is favorable for the poly-depletion effects.

[0041] A third resistor tub 34 may be embedded in the second resistorwell 12 to create a resistor ballasted FET as shown in FIG. 2. Resistorballasting is a common technique used for ESD protection and makes thedesign more compact. FIG. 3 is a schematic of the resistor ballasted FETof FIG. 2.

[0042] The present invention can also be used as a resistor/capacitorgate triggered FET. In the conventional RC triggered FET circuit, thecapacitor and resistor are external to the FET and connected by wiring.In the present invention as shown in FIG. 4, the overlapping region 22between the gate 32 and drain 30, creates a variable capacitance whichcan be tailored as needed for the RC triggered NFET. The junction depthof the second resister well 12 can be tailored to adjust resistanceneeded for the RC circuit. FIG. 5 is a schematic of this circuit.

[0043] As shown in FIGS. 6 and 7, a silicide blocking mask 36 isdeposited over the first and second resistor wells 10, 12. The silicideblocking mask 36 helps decrease the current density at the surfaceincreasing second trigger current. The silicide blocking mask 36 alsoresults in the elimination of localized hot spots (thin spots ofsilicide thickness) occurring in a silicided process. The use of thesilicide blocking mask 36 is a standard embodiment and can be used incombination with any one of the DRC-MOSFET configurations previouslydescribed.

[0044] In a standard MOSFET, the extension region is about 0.1 um deepand the source/drain region about 0.2 um deep. In the present invention,the junction depths of the resistor wells is preferably about 0.18 um,or more preferably from about 1.5 to 2 times the junction depth of astandard MOSFET n+ junction, or approximately 0.40 um.

[0045] The proposed invention provides the advantage of allowing thedevice to operate at a lower temperature during an ESD event due to thereduced current density through the higher doped, deeper junctions,which form the emitter/collector regions. Current density and jouleheating through the shallow emitter area during an ESD event is reduced,all without the need for additional masks.

[0046] While the present invention has been particularly described, inconjunction with a specific preferred embodiment, it is evident thatmany alternatives, modifications and variations will be apparent tothose skilled in the art in light of the foregoing description. It istherefore contemplated that the appended claims will embrace any suchalternatives, modifications and variations as falling within the truescope and spirit of the present invention.

Thus, having described the invention, what is claimed is:
 1. A non-selfaligned MOSFET transistor for ESD protection comprising: (a) a substratehaving a source diffusion region and a drain diffusion region; (b) afirst and second resistor well implant; (c) said first resistor wellimplanted into said source diffusion region on said substrate forming afirst resistor well having a junction depth extending into saidsubstrate; (d) said second resistor well implanted into said draindiffusion region on said substrate forming a second resistor well havinga junction depth extending into said substrate; (e) said first resistorwell and second resistor well being spaced apart to define a channelregion there between; (f) said channel region connecting said first andsecond resistor wells; (g) a gate oxide layer overlying said channel;and (h) a gate electrode overlying said oxide layer.
 2. The MOSFETstructure of claim 1, wherein said gate oxide layer and gate electrodeform a gate.
 3. The MOSFET structure of claim 1, further comprising: (i)an N-extension mask placed over said gate electrode and implanted intosaid gate.
 4. The MOSFET structure of claim 1, wherein the gate oxidelayer is silicon oxide.
 5. The MOSFET structure of claim 1, wherein thegate electrode is polysilicon.
 6. The MOSFET structure of claim 1,wherein said gate oxide layer and gate electrode extend on top of andoverlap said first and second resistor wells forming a first and secondoverlap region.
 7. The MOSFET structure of claim 6, wherein the amountof the overlap of the first and second overlap regions is variable. 8.The MOSFET structure of claim 1, wherein the junction depth of saidfirst and second resistor wells is variable.
 9. The MOSFET structure ofclaim 8, wherein a silicide blocking mask is deposited above said firstand second resistor wells thereby inhibiting the formation of silicideand deepening the junction depths of the first and second resistorwells.
 10. The MOSFET structure of claim 1, wherein the junction depthsof the first and second resistor well extend to approximately 0.40 um.11. The MOSFET structure of claim 1, further comprising a third resistortub overlying and embedded in said second resistor well to form aresistor ballasted NFET.
 12. The MOSFET structure of claim 7, wherein avariable capacitor is formed between said gate electrode and draindiffusion region by the overlap in the second overlap region.
 13. TheMOSFET structure of claim 12, wherein a variable resistor-capacitorcontrolled network is formed on the gate electrode of the MOSFET by saidvariable capacitor in combination with said first resistor well.
 14. Amethod of manufacturing a non-self aligned MOSFET transistor for ESDprotection comprising the steps of: a) providing a substrate having asource diffusion region and a drain diffusion region; b) implanting afirst resistor tub into said source diffusion region forming a firstresistor well having a first junction depth; c) implanting a secondresistor tub into said drain diffusion region forming a second resistorwell having a second junction depth, said first resistor well separatedfrom said second resistor well by a channel region there between; d)depositing a gate oxide layer and gate electrode to form a gate.
 15. Themethod of claim 14, wherein in step (d), the gate oxide layer is siliconoxide and said gate electrode is polysilicon.
 16. A method of claim 14,wherein in step (d) the gate oxide layer is extended onto and overlapssaid first and second resistor wells to define a first and secondoverlap region.
 17. The method of claim 14, further comprising extendingthe first and second junction depth to approximately 0.40 uM.
 18. Themethod of claim 14 further comprising the steps of (e) forming ann-extension mask over the top of the gate electrode and implanted saidmask into said gate.
 19. The method of claim 14, further comprising thestep, between steps (c) and (d), of depositing a silicide blocking maskover the first and second resistor wells, said blocking mask inhibitingthe formation of silicide and thereby deepening the junction depths ofthe first and second resistor wells.
 20. The method of claim 14, furthercomprising the step of overlying and embedding a third resistor tub inthe second resistor well to form a resistor ballasted NFET.